D D D D D D D Automatic powerĆdown when deselected CMOS for optimum speed/power High speed Ċ 20 ns Low active power Ċ 550 mW Low standby power Ċ 110 mW TTLĆcompatible in.

the memory location specified on the adĆ dress pins (A 0 through A 10). ReadingthedeviceisaccomplishedbytakĆ ing chip enable (CE) and output enable (OE) LOW while write enable (WE ) reĆ mains HIGH.Undertheseconditions,the contents of the memory loca.

6116LA

6116SA

61113

61113-001

61113-002

61113-003

61113-004

61113-005

6118

61-238-RSGCBKC-B02-ET

610-14-CC-D

610-xx-CC-x

610-xx-CJ-x